1. Field of the Invention
This invention relates to a digital demodulator for demodulating received signals for satellite communications, land-mobile communications, or land-mobile satellite communications.
2. Description of the Prior Art
Recently, digital demodulators have been developed in order to demodulate digitally modulated signals. Such a digital demodulator demodulates a received signal by subjecting the signal to analog-to-digital conversion, and computer-processing a digitized signal.
One such digital demodulator is described in "A New Coherent Demodulation Technique for Land-Mobile Satellite Communications" (S. Yoshida, H. Tomita, International Mobile Satellite Conference, Ottawa, pp 662-627, 1990).
FIG. 6 is a block diagram showing the configuration of this digital demodulator. The digital demodulator is used to coherently detect a QPSK-modulated signal. An IF (intermediate frequency) signal obtained by frequency-converting a received signal is inputted into the digital demodulator.
Referring to FIG. 6, an analog-to-digital converter 60 (called the "A/D converter 60") directly samples the input IF signal at a high sampling rate which is four times the rate of the IF signal frequency, and digitizes the IF signal. A digital quadrature detector 62 multiplies a sample signal (outputted from the A/D converter 60) by two reference signals, which have a fixed frequency and phases different from each other by .pi./2, or subjects the sample signal to the quasi-coherent quadrature detection. The digital quadrature detector 62 samples detected results, and generates an output signal (a detected sample signal) having a bit rate approximately four times the bit rate of the received signal. Thus, the detected sample signal is expressed by: EQU I.sub.qc (nT)=I(nT)cos(.DELTA..omega.nT+.theta.)-Q(nT)Sin(.DELTA..omega.nT+.theta.) EQU Q.sub.qc (nT)=Q(nT)cos(.DELTA..omega.nT+.theta.)-I(nT)Sin(.DELTA..omega.nT+.theta.) (1)
where I.sub.QC ( ) and Q.sub.QC ( ) respectively denote in-phase component and quadrature components of the detected sample signal; I( ) and Q( ) respectively denote in-phase components and quadrature components of the original digital signal to be transmitted; n is an integer; T denotes an interval between two sample times for the digital quadrature detector 62 to output detected sample signals; .DELTA..omega. denotes a frequency deviation between a carrier of the received signal and a frequency of the reference signal; and .theta. denotes an initial phase of the detected sample signal (i.e. an initial phase of the reference signal with respect to the received carrier). Further, the reference signals used for quasi-coherent detection have sine waves whose frequencies approximate to the frequencies of the carrier, so that the detected sample signal is a baseband signal.
The digital quadrature detector 62 outputs the detected sample signal, as complex data, to a receiving filter 64. The receiving filter 64 shapes a waveform of the detected sample signal, thereby eliminating out-of-band noise components therefrom.
An output signal from the receiving filter 64 is applied to a bit timing recovery (BTR) 66, and to an interpolator 68.
The BTR 66 determines bit timing, i.e. decision timing for deciding a value of the received signal. Information on the determined decision timing is inputted into the interpolator 68. One example of a method of estimating the decision timing by the BTR 66 is also described in the foregoing literature (by Yoshida et al.).
The output signal of the receiving filter 64 is a signal sampled at oversampling timing, which is not always synchronous with the decision timing. Therefore, the interpolator 68 interpolates this output signal, and generates a decision timing signal expressed by: EQU I.sub.N (mT.sub.S)=I(mT.sub.S)cos(.DELTA..omega.mT.sub.S +.theta..sub.N)-Q(mT.sub.S)Sin(.DELTA..omega.mT.sub.S+.theta..sub.N) EQU Q.sub.N (mT.sub.S)=Q(mT.sub.S)cos(.DELTA..omega.mT.sub.S +.theta..sub.N)+I(mT.sub.S)Sin(.DELTA..omega.mT.sub.S +.theta..sub.N)(2)
where I.sub.N ( ) and Q.sub.N ( ) respectively denote in-phase components and quadrature components of the decision timing signal; T.sub.S denotes an interval between decision times (i.e. Nyquist interval); and .theta..sub.N denotes an initial phase component of the decision timing signal.
The interpolator 68 outputs the foregoing decision timing signal as the complex data at each Nyquist interval. The following circuits operate in response to the decision timing signal. In FIG. 6, a solid line represents a route for signals which vary at each oversampling interval, while a double-solid line represents a route for signals which vary at the decision timing, i.e. vary at the Nyquist intervals.
In the circuits following the interpolator 68, a phase rotation component, which is caused by the frequency deviation (.DELTA..omega.) and the initial phase (.theta..sub.N), is eliminated from the decision timing signals I.sub.N (mT.sub.S) and Q.sub.N (mT.sub.S), thereby recovering original digital signals I(mT.sub.S) and Q(mT.sub.S).
First of all, an automatic frequency controller (AFC) 70 estimates a frequency deviation component, and feeds it back to a multiplier 72, which eliminates the frequency deviation component from the decision timing signals I.sub.N and Q.sub.N. Then, a phase estimator 74 estimates an initial phase .theta..sub.N on the basis of the decision timing signal whose frequency deviation component has been eliminated, and generates a phase correcting signal on the basis of the initial phase .theta..sub.N. The foregoing literature (by Yoshida et al.) describes an example of the internal configuration of the phase estimator 74. A multiplier 76 multiplies the decision timing signal (free from the frequency deviation component) by the phase correcting signal, thereby eliminating the initial phase component from the decision timing signal. An output of the multiplier 76 serves as a coherently detected output for the received signal.
In the digital demodulator of FIG. 6, the AFC and the phase estimator operate in response to the decision timing signal. Therefore, when a burst signal or the like is inputted, neither the AFC nor the phase estimator can operate until the BTR operates stably. In other words, even when the AFC and the phase estimator are operated, no correct output is obtainable before the stable operation of the BTR. In this state, it is meaningless to operate the AFC and so on. In the prior art, the AFC is activated after the stable operation of BTR. The phase estimator is not activated until the AFC operates stably. Therefore, the digital demodulator of the prior art is prone to a problem that it cannot satisfy a request for high speed operation. Further, even when such a digital demodulator becomes stable, malfunction of the BTR would lead to erroneous operation of the phase estimator.